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data sheet, v2.2, july 2004 never stop thinking. hye18p32161ac-70/l70 hye18p32161ac-85/l85 32m asynchronous/page cellularram cellularram memory products
edition 2004-7-12 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain comp onents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet, v2.2, july 2004 never stop thinking. hye18p32161ac-70/l70 hye18p32161ac-85/l85 32m asynchronous/page cellularram cellularram memory products
template: mp_a4_v2.0_2003-06-06.fm hye18p32161ac-70/l70, hye18p32161ac-85/l85 revision history: 2004-7-12 v2.2 previous version: 1.9 (target data sheet) page subjects (major changes since last revision) all 2nd bin of icc2 added. marking for low-power part puts ?l? in the place of ?-? all tlz, tblz, tolz are adjusted previous version: 2.0, 2.1 (target data sheet) all specified min. duration of dpd mode to be 1ms 19, 21 changing inter-page address, a4-a19 should come with cs1 toggling in page read mode 31 specified detailed timing requirement of s/w register entry mode we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 hye18p32161ac(-/l)70/85 ball configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 hye18p32161ac(-/l)70/85 ball definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 power-up and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 access to the control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 refresh control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.1 partial array self refresh (pasr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.2 deep power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.3 temperature compensated self refresh (tcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.4 power saving potentia l in standby when applying pasr, tcsr or dpd . . . . . . . . . . . . . . . . . . . 18 2.3.5 page mode enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4 asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.1 page read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.6 deep power down mode entry/ exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.7 general ac input/output reference waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 recommended power & dc operation ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 3.3 output test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 appendix a: s/w register entry mode (?4-cycle method?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
hye18p32161ac(-/l)70/85 32m asynch/page cellularram data sheet 6 v2.2, 2004-7-12 figure 1 cellularram - interface configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 standard ballout - hye18p32161ac(-/l)70/85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5 refresh control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6 control register write access protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7 pasr programming scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8 pasr configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9 asynchronous read - address controlled (cs1 = oe = v il , we = v ih , ub and/or lb = v il , zz = v ih ) 20 figure 10 asynchronous read (we = v ih , zz = v ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11 asynchronous page read mode (zz = v ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12 asynchronous write - we controlled (oe = v ih or v il , zz = v ih ) . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13 asynchronous write - cs1 controlled (oe = v ih or v il , zz = v ih ) . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14 asynchronous write - ub , lb controlled (oe = v ih or v il , zz = v ih ) . . . . . . . . . . . . . . . . . . . . . . 24 figure 15 asynchronous write to control register (oe = v ih or v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 16 deep power down entry/ exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17 output test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18 p-vfbga-48 (plastic very thin fine pitch ball grid array package) . . . . . . . . . . . . . . . . . . . . . . 29 figure 19 s/w register entry timing (address input = 1fffffh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 20 rcr mapping in s/w register entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
data sheet 7 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram table 1 product selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2 ball description - hye18p32161ac(-/l)70/85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3 asynchronous command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4 description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5 standby currents when applying pasr, tcsr or dpd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6 timing parameters - asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7 timing parameters - asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8 dpd/ zz timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12 operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
data sheet 8 v2.2, 2004-7-12 32m asynchronous/page cellularram cellularram hye18p32161ac-70/l70 hye18p32161ac-85/l85 1overview 1.1 features high density (1t1c-cell) asynchronous 32-mbit pseudo-static ram designed for cell phone applications (cellularram) functional-compatible to conventional low power asynchronous sram devices organization 2m 16 refresh-free operation 1.8 v single power supply ( v dd and v ddq ) support of 2.5v and 3.0v i/o voltage options ( v ddq ) low power optimized design ? i standby = 90 a for l-part and 120 a for standard part (32m), data retention mode ? i dpd = < 25 a (32m), non-data retention mode low power features (partly adopted from the jedec standardized low power sdram specifications) ? temperature compensated self-refresh (tcsr) ? partial array self-refresh (pasr) ? deep power down mode (dpd) 70 ns random access cycle time, 20 ns page mode (read only) cycle time byte read/write control by ub /lb wireless operating temperature range from -25 c to +85 c p-vfbga-48 chip-scale package (8 6 ball grid) table 1 product selection hye18p32161ac -70 -85 l70 l85 min. random cycle time (trc) 70ns 85ns 70ns 85ns min. page read cycle time (tpc) 20ns 25ns 20ns 25ns operating current (icc1) 20ma 17ma 20ma 17ma stand-by current (icc2) 120ua 90ua ordering info (contact factory) hye 18 p 3216 1 a c chip scale package design revision number device type 32m (x16 org) v dd = 1.8 v typ. psram product 1: asynch/page (48-ball) extended temp. part
data sheet 9 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram overview 1.2 general description the 32m asynchronous/page ce llularram (cellularram) is is the competitive alternat ive to today?s sram based solutions in wireless applic ations, such as cellular phones. with its high density 1t1c-cell concept and highly optimized low power design, the cellularram is the advanced economic solution for the growing memory demand in baseband ic designs. sram-pin co mpatibility, refres h-free operation and extrem e low power design makes a drop-in replacement in legacy systems an easy procedure. low power feature of partial array self refresh (pasr ) allows the user to dy namically scale the active (=refreshed) memory to his needs and to adapt the refresh rate to the actual system environment. that is no power penalty is paid in case only portions of the total ava ilable memory capacity is used (e.g. 8mb out of 32mb). the cellularram is available in two package options, in the sram compatible fbga 48-ball package and with an enhanced feature set in a fbga 54-ball package. for the advanced 54-ball device please refer to the corresponding data sheet ( hye18p32160ac) . the celllularram can be powered from a single 1.8v power supply feedi ng the core and th e output drivers. feeding the i/os with a separate volt age supply the celllularram can be ea sily adapted to systems operating in an i/o voltage range from 1.8v to 3.0v. the chip is fabricated in infineon technol ogies advanced 0.14m low power process technology. the configuration of interfacing cellularram is illustrated in figure 1 . data byte control (ub , lb ) is featured in all modes and provides dedicated lower and upper byte access. figure 1 cellularram - interface configuration options the cellularram comes in a p-vfbga-48 package. fbga-48 cs1 we oe ub lb zz a20-a0 dq15-dq0 fbga-48 a20-a0 dq15-dq0 1.8v vdd & vddq 1.8v vdd 2.5v/ 3.0v vddq cs1 we oe ub lb zz
hye18p32161ac(-/l)70/85 32m asynch/page cellularram overview data sheet 10 v2.2, 2004-7-12 1.3 hye18p32161ac(-/l)70/85 ball configuration figure 2 standard ballout - hye18p32161ac(-/l)70/85 note: figure 2 shows top view lb 123 d b c h e f g a0 a 6 45 dq 8 a1 oe ub a2 zz a3 a4 cs1 dq 0 dq 9 dq 10 a5 a6 dq 1 dq 2 v dd dq 3 a7 a17 dq 11 dq 12 nc (a21) a16 dq 13 dq 14 a14 a15 a13 a8 a19 a12 dq 15 a18 a9 a10 dq 4 dq 5 we dq 7 a20 a11 v ssq v ddq v ss dq 6
data sheet 11 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram overview 1.4 hye18p32161ac(-/l)70/85 ball definition and description table 2 ball description - hye18p32161ac(-/l)70/85 ball type detailed function cs1 input chip select cs1 enables the command decoder when low and disables it when high. when the command decoder is disabled new commands are ignored, addresses are don?t care and outputs are forced to high-z. internal operations, however, continue. for the details please refer to the command tables in chapter 1.6 . oe input output enable oe controls dq output driver. oe low drives dq, oe high sets dq to high-z. we input write enable we set to low while cs is low initiates a write command. ub , lb input upper/lower byte enable ub enables the upper byte dq15-8 (resp. lb dq7 ? 0) during read/write operations. ub (lb ) deassertion prevents the upper (lower) byte from being driven during read or being written. zz input deep power down enable/ set control register strapping zz to low for more than 10s the device is put to deep power down mode. if a write access is initiated in stantly (<500ns) after zz has been asserted to low access to the refresh configuration register is given. by appl ying the set control register (scr) command (see table 3 ) the address bus is then loaded into the refresh control register. a <20:0> input address inputs during a control register set operation, the address inputs define the register settings. dq <15:0> i/o data input/output the dq signals 0 to 15 form the 16-bit data bus. 1 v dd 1 v ss power supply power supply, core power and ground for the internal logic. 1 v ddq 1 v ssq power supply power supply, i/o buffer isolated power and ground for the output buffers to provide improved noise immunity. 1 nc ? no connect please do not connect. reserved for future use, i.e. e3: a21, see ballout in figure 2 on page 10 .
hye18p32161ac(-/l)70/85 32m asynch/page cellularram overview data sheet 12 v2.2, 2004-7-12 1.5 functional block diagram figure 3 functional block diagram address decode asynchronous sram i/f 1t1c cell memory array 2m x16 control logic cs1 we oe ub lb zz a20-a0 dq15-dq8 dq7-dq0
data sheet 13 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram overview 1.6 commands all commands are of asynchronous nature. the supported co ntrol signal combinations ar e listed in the table below. c note: ?l? represents a lo w voltage level, ?h? a high voltage level, ?x? re presents ?don?t care?, ?v? represents ?valid?. note: ?l? represents a lo w voltage level, ?h? a high voltage level, ?x? re presents ?don?t care?, ?v? represents ?valid?. table 3 asynchronous command table operation mode power mode cs1 we oe ub /lb zz a19 a20 - a0 dq15:0 read active l h l l 1) 1) table 3 reflects the behaviour if ub and lb are asserted to low. if only either of the signals, ub or lb , is asserted to low only the corresponding data byte will be output or written (ub enables dq15 - dq8, lb enables dq7 - dq0). hv adr dout write active l l x 2) 2) during a write access invoked by we set to low the oe signal is ignored. l 1) hv adr din set control register active l l x 2) xllrcr din x no operation standby~active 3) 3) stand-by power mode applies only to the case when cs goes low from deselect while no address change occurs. toggling address results in active power mode. also, no operation from any active power mode by keeping cs low consumes the power higher than stand-by mode. l h h x h x x high-z deselect standby h x x x x x x high-z dpd deep power down h x x x l x x high-z table 4 description of commands mode description read the read command is used to perform an asyn chronous read cycle. the signals, ub and lb , define whether only the lower, the upper or the whole 16-bit word is output. write the write command is used to perform an asynchronous write cycle. the data is latched on the rising edge of either cs , we , ub , lb , whichever comes first. the signals, ub and lb , define whether only the lower, the upper or the whole 16-bit word is latch ed into the cellularram. set control register the control registers are loaded via the address inputs a15 - a0 performing an asynchronous write access. please refer to the control register description for details. the scr command can only be iss ued when the cellularram is in idle state. no operation the nop command is used to perform a no operation to the cellularram, which is selected (cs1 = 0). operations already in progress are not affected. power consumption of this command mode varies by address change and initiating condition. deselect the deselect function prevents ne w commands from being executed by the cellularram. the cellularram is effectiv ely deselected. i/o signals are put to high impedance state. dpd dpd stops all refresh-related activiti es and entire on-chip circuit operation. current consumption drops below 25 a. wake-up from dpd also requires 150 s to get ready for normal operation. it is prohibited to invoke the dpd mode which only lasts no longer than 1ms.
hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description data sheet 14 v2.2, 2004-7-12 2 functional description 2.1 power-up and initialization the power-up and initialization sequence guarantees that the device is preconditioned to the user?s specific needs. like conventional drams, the cellularram must be powered up and initialized in a predefined manner. v dd and v ddq must be applied at the same time to the specified voltage while the input signals are held in ?deselect? state (cs1 = high). after power on, an initial pause of 150 s is required prior to the control register access or normal operation. failure to follow these steps may lead to unpredictable start-up modes. figure 4 power up sequence vdd, vddq t pu =150 s ready for normal operation vdd,vddq,min
data sheet 15 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description 2.2 access to the contro l register map write-only access to the refresh control register is enabled by applying the scr command and asserting the zz - pin to low. figure 5 shows the mapping of the address bus lines to the the refresh control register bits, whereas in figure 6 the access timing is illustrated. figure 5 refresh control registers figure 6 control register write access protocol pasr refreshed memory area a2 a1 a0 partial array self refresh 001 010 a0 entire memory array (def.) 000 a1 a2 a3 a4 a5 a6 a7 a8 a18 a20 tcsr pm 0 0 0 max. case temp. a5 temperature-compensated self-refresh 1 +85c (def.) +70c +45c +15c 0 1 0 a6 1 0 0 1 control reg control register select rcr reserved 0 1 a19 address bus control register power down deep power down mode enabled disabled (def.) 0 1 a4 011 lower 1/2 of memory array lower 1/4 of memory array lower 1/8 of memory array 101 110 111 upper 1/2 of memory array upper 1/4 of memory array upper 1/8 of memory array dpd 0 zero 100 page mode page mode bit disabled (def.) enabled 0 1 a7 a19 0 a20, a18....a8, a3: reserved, must be set to '0'. don't care a20-a0 rcr opcode cs1 we ub, lb dq15-dq0 zz initiate control register access open latch close latch
hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description data sheet 16 v2.2, 2004-7-12 2.3 refresh control register the refresh control register (rcr) allows to save stand-by power additionally by making use of the temperature-co mpensated self refresh (tcs r), partial-array self refr esh (pasr) and deep power down (dpd) features. the refresh control register is progra mmed via the control register set command and retains the stored information until it is reprogrammed or the device loses power. please note that the rcr contents can only be set or changed when the cellularram is in idle state. rcr refresh control register (zz , a19 = 00 b ) a20a19a18a17a16a15a14a13a12a11a10a9a8a7a6a5a4a3a2a1a0 0 rs 0 pm tcsr dpd 0 pasr field bits type 1) description rs 19 w register select 0 set to 0 to select this rcr. pm 7 w page mode enable/disable in asynchronous operation mode the user has the option to toggle a0 - a3 in a random way at higher rate (20 ns vs. 70 ns) to lower access times of subsequent reads with 16-word boundary. in synchronous mode this option has no effect. the max. page length is 16 words. please note that as soon as page mode is enabled the cs1 low time restriction applies. this means that the cs1 signal must not be kept low longer than t csl = 8 s. please refer to figure 11 . 0 page mode disabled (default) 1 page mode enabled tcsr [6:5] w temperature compensated self refresh the 2-bit wide tcsr field features four different temperature ranges to adjust the refresh period to the actual case temperature. since dram technology requires higher refresh rates at higher temperature this is a second method to lower power consumption in case of low or medium temperatures. 11 +85 c (default) 00 +70 c 01 +45 c 10 +15 c dpd 4 w deep power down enable/disable the dpd control bit puts the cellularram device in an extreme low power mode cutting current consumption to less than 25 a. stored memory data is not retained in this mode, while the settings of cont rol register, rcr is stored during dpd. please note that it is not allowed to use dpd mode for the duration of less than 1ms. 0 dpd enabled 1 dpd disabled (default)
data sheet 17 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description 2.3.1 partial array self refresh (pasr) by applying pasr the user ca n dynamically customize the memory capa city to one?s actual needs in normal operation mode and standby mode. with the activation of pasr there is no longer a power penalty paid for the larger cellularram memory capacity in case only e.g. 8 mb are used by the host system. bit2 down to bit0 specify the active memory array and its location (starting from bottom or top). the memory parts not used are powered down immediately after the mode register has been programmed. advice for the proper register setting including the address ranges is given in figure 7 . figure 7 pasr programming scheme pasr is activated, i.e. the memory parts not used are powered down, after zz has been held low for more than 10s. in pasr state no read or write commands are recognized. to resume write or read operations, the device must exit pasr by taking zz to high level voltage again. pre-condition to enter pasr on zz low is that the deep power down mode has been disabled before via rcr.bit4= 1. figure 8 shows an exemplary pasr configuration where it is assumed that the application uses max. 8 mbit out of 32 mbit. pasr [2:0] w partial array self refresh the 3-bit pasr field is used to specify the acti ve memory array. the active memory array will be kept periodically refreshed wh ereas the disabled parts will be excluded from refresh and previously stored data will get lost. the normal operation still can be executed in disabled array, but stored data is not guaranteed. this way the customer can dynamically adapt the memory capacity in steps of 8 mbit (4mbit at the lowest) to one?s need without paying a power penalty. please refer to figure 7 . 000 entire memory array (default) 001 lower 1/2 of the memory array (16 mb) 010 lower 1/4 of the memory array (8 mb) 011 lower 1/8 of the memory array (4 mb) 100 zero 101 upper 1/2 of the memory array (16 mb) 110 upper 1/4 of the memory array (8 mb) 111 upper 1/8 of the memory array (4 mb) res 20, [18:8], 3 w reserved must be set to ?0? 1) w: write-only access field bits type 1) description 8m 8m 8m 8m 000000h 07ffffh 0fffffh 17ffffh 1fffffh 000 001 010 011 1fffffh 180000h 100000h 080000h 000000h 100 101 110 111 pasr.bit2,1,0 pasr.bit2,1,0 4m 8m 16m 32m 4m 8m 16m 0m
hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description data sheet 18 v2.2, 2004-7-12 figure 8 pasr configuration example 2.3.2 deep power down mode to put the device in deep power down mode, it is required to comply with 2-steps. at first, the dpd mode bit must be set to be enabled in the refresh configuration register. when dpd entry is really required, zz pin must be asserted to low for longer than 10s. between these 2 steps, any normal operations are permitted. once the device enters into this extreme low power mode, current consumption is cut down to less than 25a. it is prohibited to use dpd mode in case the duration does not exceed 1ms. all internal voltage ge nerators inside the celllularram are switched of f and the internal self -refresh is stopped. this means that all stored information will be lost in any time. the devi ce will remain in dpd mode as long as zz is held low.to exit the deep power down mode, it is needed to simply bring zz to high voltage level. a guard time of at least 150s has to be met wh ere no commands beside deselect must be applied to re-enter standby or idle mode. (see figure 16 ) . 2.3.3 temperature compensat ed self refresh (tcsr) the 2-bit wide tcsr field features four different temperatur e ranges to adjust the refresh period to the actual case temperature. dram technology requires higher refresh rates at higher temperature. at low temperature the refresh rate can be reduced, which reduces as well the standby current of the chip. this feature can be used in addition to par to lower power consumption in case of low or medium temperatures. please refer to table 5 . 2.3.4 power saving potential in standby when applying pasr , tcsr or dpd table 5 demonstrates the cu rrents in standby mode when pasr, tcsr or dpd is applied. this is for reference only. it is not 100% tested, only sampled. table 5 standby currents when applying pasr, tcsr or dpd operation mode power mode pasr bit controlled wake-up phase active array standby [ a] no operation/ deselect standby tcsr rcr.bit6-5 ? ? 85 70 45 15 pasr rcr.bit2-0 ? full 1/2 1/4 1/8 0 90(120) 80(105) 70(90) 60(75) 50(60) 75(100) 68(90) 62(80) 55(70) 50(60) 60(80) 56(75) 53(70) 52(65) 50(60) 50(60) 50(60) 50(60) 50(60) 50(60) dpd deep power down dpd rcr.bit4 ~150 s0 25.0 24mb deactivated 000000h 07ffffh rcr.bit 2,1,0= 010 active memory array defined by pasr to 8mb 8m activated 32mb cellularram
data sheet 19 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description 2.3.5 page mode enable/disable in asynchronous operation mode, the user has the option to enable page mode to toggle a0 - a3 in random way at higher cycle rate (20 ns vs. 70 ns) to lower access times of subsequent reads within 16-word boundary. write operation is not supported in the manner of page mode access. in synchronous mode, this option has no effect. the max. page length is 16 words, so which a0 - a3 is regarded as page-mode address. if the access needs to cross the boundary of 16-word (any difference in a20 - a4 ), then it should start over new random access cycle with toggling cs1 . please note that as soon as page mode is enabled the cs1 low time restriction applies. this means that the cs1 signal must not kept low longer than t csl = 8 s. please refer to figure 11 .
hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description data sheet 20 v2.2, 2004-7-12 2.4 asynchronous read the cellularram applies the standard asynchronous sram protocol to perform read and write accesses. reading from the device in asynchronous mode is accomplished by asserting the chip select (cs1 ) and output enable (oe ) signals to low while forcing write enable (we ) to high. if the upper byte (ub ) control line is set active low then the upper word of the addressed data is driven on the output lines, dq15 to dq8. if the lower byte (lb ) control line is set active low then the lower word of the add ressed data is driven on the output lines, dq7 to dq0. figure 9 asynchronous read - address controlled (cs1 = oe = v il , we = v ih , ub and/or lb = v il , zz = v ih ) figure 10 asynchronous read (we = v ih , zz = v ih ) not valid a20-a0 address data valid dq15-dq0 previous data t oh t aa t rc don't care a20-a0 address cs1 ub, lb oe data valid we dq15-dq0 t co t aa t ba t oe t blz t oh t ohz t bhz t rc t hz t olz t lz t cph t bph
data sheet 21 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description 2.4.1 page read mode if activated by rcr.bit7 page mode allows to toggle the four lower address bits (a3 to a0) to perform subsequent random read accesses (max. 16-words by a3 - a0) at much faster speed than 1 st read access. page mode operation supports only read access in cellularr am. as soon as page mode is activated, cs1 low time restriction ( t csl ) applies. toggling cs1 is required to start over new page when a4 or higher addresses change. the usage of page mode is only recommended in systems which can respect this limitation. figure 11 asynchronous page read mode (zz = v ih ) don't care a20-a4 address cs1 ub, lb oe we dq15-dq0 t co t lz t blz t bhz t ohz t rc a3-a0 address t aa data adr adr adr adr t paa t csl t olz t hz t pc data data data data t oh
hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description data sheet 22 v2.2, 2004-7-12 table 6 timing parameters - asynchronous read parameter symbol 70 85 unit notes min. max. min. max. read cycle time t rc 70?85?ns? address access time t aa ?70?85ns? page address cycle time t pc 20?25?ns? page address access time t paa ?20?25ns? output hold from address change t oh 5?6?ns? chip select access time t co ?70?85ns? ub , lb access time t ba ?70?85ns? oe to valid output data t oe ?20?25ns? chip select pulse width low time t csl ?8?8 s? chip select to output active t lz 6?6?ns? chip select disable to high-z output t hz ?10?10ns? ub , lb enable to output active t blz 5?5?ns? ub , lb disable to high-z output t bhz ?9?9ns? output enable to output active t olz 3?3?ns? output disable to high-z output t ohz ?6?8ns? cs1 high time when toggling t cph 10?15?ns? ub , lb high time when toggling t bph 10?15?ns?
data sheet 23 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description 2.5 asynchronous write writing to the device in asynchronous mode is accomplished by asserting the chip select (cs1 ) and write enable (we ) signals to low. if the upper byte (ub ) control line is set active low then the upper word (dq15 to dq8) of the data bus is written to the specified me mory location. if the lower byte (lb ) control line is set active low then the lower word (dq7 to dq0) of the data bus is written to the specified memory location. write operation takes place when either one or both ub and lb is asserted low. the data is latched by the rising edge of either cs1 , we , or ub /lb whichever signal comes first. figure 12 asynchronous write - we controlled (oe = v ih or v il , zz = v ih ) figure 13 asynchronous write - cs1 controlled (oe = v ih or v il , zz = v ih ) don't care a20-a0 address cs1 we ub, lb dqx out t cw t wr t wc t wp t aw t bw data valid dqx in t dw t dh t as t whz t ow t wph don't care a20-a0 address cs1 we ub, lb dqx out t cw t wr t wc t wp t aw t bw data valid dqx in t dw t dh t as t whz t cph
hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description data sheet 24 v2.2, 2004-7-12 figure 14 asynchronous write - ub , lb controlled (oe = v ih or v il , zz = v ih ) the programming of control register in asynchronous mode is performed in the similar manner as asynchronous write except zz being held low during the operation. note that zz has to meet set-up time ( t zzwe ) and hold time ( t wezz )of valid state (= low) in reference to we falling and rising edge, respectively. cs1 should toggle at the end of the operation to get ready for following access. figure 15 asynchronous write to control register (oe = v ih or v il ) don't care a20-a0 address cs1 we ub, lb dqx out t cw t wr t wc t as t wp t aw t bw data in valid dqx in t dw t dh high-z t blz, t lz t whz t bph don't care a20-a0 rcr opcode cs1 we ub, lb dqx out t cw t wr t wc t wp t aw dqx in t as zz t zzwe t cdzz high-z high-z t wph t wezz
data sheet 25 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description table 7 timing parameters - asynchronous write parameter symbol 70 85 unit notes min. max. min. max. write cycle time t wc 70?85?ns? address set-up time to start of write t as 0?0?ns? address valid to end of write t aw 70?85?ns? write recovery time t wr 0?0?ns? chip select pulse width low time t csl ?8?8 s? chip select to end of write t cw 70?85?ns? byte control valid to end of write t bw 70?85?ns? write pulse width t wp 40?45?ns? write pulse pause t wph 10?15?ns? cs high time when toggling t cph 10?15?ns? ub , lb high time when toggling t bph 10?15?ns? write to output disable t whz ?10?10ns? end of write to output enable t ow 3?3?ns? write data setup time t dw 20?20?ns? write data hold time t dh 0?0?ns? cs1 high setup time to zz low t cdzz 5?5?ns? zz active setup time to start of write t zzwe 1050010500ns? zz active hold time from end of write t wezz 0?0?ns?
hye18p32161ac(-/l)70/85 32m asynch/page cellularram functional description data sheet 26 v2.2, 2004-7-12 2.6 deep power down mode entry/ exit to put the device in deep power down mode, it is required to comply with 2-step operation. at first, the dpd mode bit (rcr.bit4) has be programmed to be enabled in the refresh configuration register through scr command. when dpd entry is really required, zz pin must be asserted to low for longer than 10s while cs1 sets to high as shown in figure 15. between these 2 steps, any normal operations are permitted. once the device enters into this extreme low power mode, current consumpt ion is cut down to less than 25a. please note that 2 step operation for dpd entry is not designed to take place at a time when zz is held low. in case of back-to-back operation to perform 2 steps, it is required to meet zz precharge time (t zph ). all internal voltage ge nerators inside the celllularram are switched off and the intern al self-refresh is stopped. this means that all stored in formation will be lost in any time. the device will remain in dpd mode as long as zz is held low. to exit the de ep power down mode, it is needed to simply bring zz to high voltage level. a guard time of at least 150s (t r ) has to be met where no co mmands beside deselect must be applied to re -enter standby or idle mode. figure 16 deep power down entry/ exit table 8 dpd/ zz timing table 2.7 general ac input/out put reference waveform the input timings refer to a midlevel of v ddq /2 while as output timings refer to midlevel v ddq /2. the rising and falling edges are 10 - 90% and < 2 ns. parameter symbol 70 & 85 unit notes min. max. cs1 high setup time to zz low t cdzz 5?ns? zz precharge time t zph 5?ns? zz active for dpd entry t zzmin 10 ? s ? dpd duration t dpd 1?ms? recovery time from dpd exit t r 150 ? s ? don't care cs1 zz t zzmin t cdzz t r exiting dpd device in dpd (maintaining) entering dpd t zph (/zz high time is required between step 1 and 2) (any normal operation is allowed in between) step 1 (scr) rcr.bit4 should be programmed to enable dpd step 2 /zz low for longer than tzzmin t dpd
data sheet 27 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram electrical characteristics 3 electrical characteristics 3.1 absolute maximum ratings attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 3.2 recommended power & dc operation ratings all values are recommended operati ng conditions unless otherwise noted. table 9 absolute maximum ratings parameter symbol limit values unit notes min. max. operating temperature range t c -25 +85 c ? storage temperature range t stg -55 +150 c ? soldering peak temperature (10 s) t sold ?260c? voltage of v dd supply relative to v ss v dd -0.3 +2.45 v ? voltage of v ddq supply relative to v ss v ddq -0.3 +3.6 v ? voltage of any input relative to v ss v in -0.3 +3.6 v ? power dissipation p d ?180mw? short circuit output current i out -50 +50 ma ? table 10 recommended dc operating conditions parameter symbol limit values unit notes min. typ. max. power supply voltage, core v dd 1.7 1.8 1.95 v ? power supply voltage, 1.8 v i/os v ddq 1.7 1.8 2.25 v ? power supply voltage, 2.5 v i/os v ddq 2.3 2.5 2.7 v ? power supply voltage, 3.0 v i/os v ddq 2.7 3.0 3.3 v ? input high voltage v ih v ddq ? 0.4 ? v ddq + 0.2 v ? input low voltage v il -0.2 ? 0.4 v ? table 11 dc characteristics parameter symbol limit values unit notes min. typ. max. output high voltage ( i oh = -0.2 ma) v oh v ddq 0.8 ? ? v ? output low voltage ( i ol = 0.2 ma) v ol ?? v ddq 0.2 v ? input leakage current i li ??1 a? output leakage current i lo ??1 a?
hye18p32161ac(-/l)70/85 32m asynch/page cellularram electrical characteristics data sheet 28 v2.2, 2004-7-12 3.3 output test conditions figure 17 output test circuit please refer to section section 2.7 . 3.4 pin capacitances table 12 operating characteristics parameter symbol 70 85 unit test condition notes min. max. min. max. operating current async read/write random @ t rcmin async read/write random @ t rc = 1 s async page read i dd1 i dd1l i dd1p ? ? ? 20 5 15 ? ? ? 17 5 12 ma v in = v dd or v ss , chip enabled, i out = 0 1) stand-by current : l-part (32m) i dd2 ?90?90 a v in = v dd or v ss , chip deselected, (full array) ? stand-by current : std. part (32m) ? 120 ? 120 a deep power down current (32m) i dd3 ?25?25 a v in = v dd or v ss ? 1) the specification assu mes the output disabled. table 13 pin capacitances pin limit values unit condition min. max. a20 - a0, cs1 , oe , we , ub , lb , zz ?5.0pf t a = +25 c freq. = 1 mhz v pin = 0 v (sampled, not 100% tested) dq15 - dq0 ? 6.0 pf 30pf test point vddq dut 5.4kohm 5.4kohm vssq vssq
data sheet 29 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram package outlines 4 package outlines figure 18 p-vfbga-48 (plastic very thin fine pitch ball grid array package) s md = surface mounted device y ou can find all of our packages, sorts of packing and others in our i nfineon internet page ?products?: http://www.infineon.com/products . dimensions in m m
data sheet 30 v2.2, 2004-7-12 hye18p32161ac(-/l)70/85 32m asynch/page cellularram appendix a: s/w register entry mode (?4-cycle method?) appendix a: s/w register en try mode (?4-cycle method?) other than zz -controlled scr operation, cellularram supports software (s/w) method as an alternative to access the control registers. since s/w register entry mo de consists of 4 consecutive access cycles to top memory location (all addresses are ?1 ?), it is often referred as ?4-cycle method? . 4-cycles starts from 2 back-to-back read cycles (initializing command identification) followed by one write cycle (command identification completed and refresh control register is accessed), then final write cycle for configuring the rcr by the given input or read cycle to check the content of the register through dq pins. it do es function the configuration of control register bits like the way with dedicated pin, zz method, but there are a few differences from zz -controlled method as follow; register read mode (checking content) is supported with s/w register entry as well as register write (program). the mode bits for control register are supplied through dq <15:0> instead of address pins in zz -controlled. though each register has 21-bits (a<20:0>) for 32mb cellularram, only low 16-bit registers becomes valid during s/w method. the valid selection of refresh control register, rcr, is done with the state of dq<15:0> given at 3rd cycle. (?00h?) since s/w register entry asks for 4 complete access cycles in a row and the device is designed operating with internally regulated supply which is going to be discharged in deep power-down (dpd) mode, dpd function is not supported with this programming method. the method is realized by the device exactly when 2 consecutive read cycles to top memory location is followed by write cycle to the same location, so that any exceptional cycle combinat ion - not only access mode, but also the number of cycles - will fail in in voking the register entry mode properly. figure 19 s/w register entry timing (address input = 1fffffh) as depicted in figure 19 , 4-cycle operation requires the following timing requirement which are not applied to normal asynchronous read or write cycles. cs has to toggle in every cycle to distinguish 4 consecutive cycles. address input of top memory location has to be maintained until the completion of each cycle by simply holding all address signals high or latching them by adv until cs goes high. don't care amax-a0 all ?1?s cs ub, lb oe we dq15-dq0 t rc adv# all ?1?s all ?1?s 0000h(rcr) all ?1?s ` register bits read to top memory location (1 st ) read to top memory location (2nd) write to top memory location write or read to top memory location (cycle type) (function) wait for next write to confirm s/w register entry select rcr (write) configure rcr by dq inputs (read) output rcr contents through dq t wc
hye18p32161ac(-/l)70/85 32m asynch/page cellularram appendix a: s/w register entry mode (?4-cycle method?) data sheet 31 v2.2, 2004-7-12 figure 20 rcr mapping in s/w register entry pasr refreshed memory area d2 d1 d0 partial array self refresh 001 010 d0 entire memory array (def.) 000 d1 d2 d3 d4 d5 d6 d7 d8 d15 tcsr pm 0 0 max. case temp. d5 temperature-compensated self-refresh 1 +85c (def.) +70c +45c +15c 0 1 0 d6 1 0 0 1 dq<15:0> control register power down deep power down mode disabled (def.) x d4 011 lower 1/2 of memory array lower 1/4 of memory array lower 1/8 of memory array 101 110 111 upper 1/2 of memory array upper 1/4 of memory array upper 1/8 of memory array dpd* 0 zero 100 page mode page mode bit disabled (def.) enabled 0 1 d7 d15....d8, d3: reserved, must be set to '0'.
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